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NXP Semiconductors /MIMXRT1064 /DCDC /REG1

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Interpret as REG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0REG_FBK_SEL 0 (REG_RLOAD_SW)REG_RLOAD_SW 0LP_CMP_ISRC_SEL 0 (LOOPCTRL_HST_THRESH)LOOPCTRL_HST_THRESH 0 (LOOPCTRL_EN_HYST)LOOPCTRL_EN_HYST 0VBG_TRIM

Description

DCDC Register 1

Fields

REG_FBK_SEL

select the feedback point of the internal regulator
REG_RLOAD_SW

control the load resistor of the internal regulator of DCDC, the load resistor is connected as default “1”, and need set to “0” to disconnect the load resistor
LP_CMP_ISRC_SEL

set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA
LOOPCTRL_HST_THRESH

increase the threshold detection for common mode analog comparator
LOOPCTRL_EN_HYST

Enable hysteresis in switching converter common mode analog comparators
VBG_TRIM

trim bandgap voltage

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data